The present invention relates to digital systems and, more particularly, to a method and apparatus for incrementally adjusting the phase of a digital signal.
A conventional timing recovery loop is illustrated in FIG. 1. FIG. 1 illustrates that a phase detector output is fed directly into a low-frequency filter.
Decisions for timing phase error calculation are based on a channel symbol detector or sequence detector. In general, the detector performance is based on the delay of the decision. The longer the decision delay, the better the decision quality. Short decision delays lead to bad decision quality. When the timing recovery loop, such as illustrated in FIG. 1, operates in a noisy channel condition, the decision error can cause timing recovery failure as a result of insufficient time or delay to make a quality decision. To prevent this failure, a detector with a longer decision delay could be used. However, this delay adds to the entire latency of the timing loop and, consequently, this delay is undesirable. Furthermore, the latency of a timing recovery loop directly affects its tracking capability to timing phase variation. A timing recovery loop with a long decision delay detector has a limited tracking capability to timing phase variation.
The present invention includes a method and apparatus for decision error compensation for a decision-directed timing recovery loop. The present invention employs a relatively short decision delay detector in combination with a longer decision delay detector. If the long decision delay detector detects a decision error, the phase error resulting from this decision error is correspondingly compensated with a new phase signal. Thus, by employing a long decision delay detector, reliable decisions can be achieved for the timing recovery loop.